It is well known that a non-volatile memory device such as a MOSFET (a “metal oxide semiconductor field effect transistor”) with a floating gate can store varying amounts of charge on the floating gate. The amount of charge stored on the floating gate alters the threshold voltage of the device (i.e., gate voltage at which the underlying MOS transistor turns on) in a well-known manner. Different amounts of charge on the floating gate correspond to different threshold voltages for the underlying MOS transistor.
Semiconductor non-volatile memories (“NVM”) and particularly electrically erasable, programmable read-only memories (“EEPROMs”) are widely used in computers, telecommunications systems, consumer appliances and other electronic equipment. An EEPROM is a particular type of non-volatile memory, which is capable of storing firmware and data even when the power to the system is turned off. Moreover, the information stored in an EEPROM can be altered, erased and replaced as needed. A flash EEPROM is a specific type of EEPROM that can be erased globally or on a sector-by-sector basis, as required.
Data is stored in an EEPROM cell by injecting charge carriers in a well-known manner into the floating gate of the MOSFET from the channel of the MOSFET or onto a charge trapping dielectric layer in between the gate and the channel of the MOSFET. The floating gate or the charge-trapping dielectric layer is sometimes called the “charge storage layer”. For example, with respect to an N-channel MOSFET, an accumulation of electrons in the floating gate (which basically comprises a conductive layer above but insulated from, the channel region of the MOSFET) increases the threshold voltage Vth required to turn on the underlying field effect transistor. Overlying but insulated from the floating gate is a conductive gate (also called the “control gate”) to which is applied a voltage which normally will cause the channel region between the source and drain of the underlying MOS field effect transistor to invert to the same conductivity type as the source and drain and thus “turn on” (i.e., allow current to flow from the source to the drain). When a fixed read voltage is applied to the gate of the MOSFET, the MOSFET will either turn on (i.e., allow current to flow from the source to the drain) or remain off depending on the value of Vth. The value of Vth is controlled by the amount of charge placed on the floating gate and the impurity concentration in the channel of the MOSFET.
Both parallel and serial sensing have been proposed for use with a non-volatile memory cell which is capable of storing a plurality of bits. In conventional sensing schemes for reading a multi-level memory cell, the current or voltage response from an NVM cell resulting from applying a fixed read voltage to the control gate is compared to reference currents or voltages generated from different threshold voltage levels of identical non-volatile memory cells under the same condition. The parallel sensing method compares the response current or voltage from the memory cell simultaneously to the reference currents or voltages and determines the bit level for the non-volatile memory cell being read from the closest match.
The serial sensing method compares the current or voltage response from the non-volatile memory cell with the variable reference response controlled by a successive approximation register (“SAR”) supplied with the output signal of a comparator. The SAR comprises a sequential network that, starting with a predetermined initial state, evolves through a succession of states, each one corresponding to one step of the serial binary search.
Basically, both parallel and serial sensing methods in the prior art compare the analog output electrical signal from a non-volatile memory cell to the analog output electrical signals from non-volatile memory cells with different threshold levels. In one system, the analog output electrical signal from a given non-volatile memory cell with a given control gate voltage is converted into a digital signature and compared to a plurality of analog electrical output signals generated from non-volatile memory cells with different threshold levels. The sense and determine scheme can be considered as a type of analog to digital converter (“ADC”). The analog electrical output signal, which provides the closest match represents the data stored on the memory cell being read and its digital counterpart is read out of the system.
Since the responses (i.e., either current or voltage) from the memory cells having multiple threshold levels under a fixed control gate voltage and fixed load condition are quite different, the previous conventional read schemes may not operate in a most optimized manner to determine the particular bits stored in a non-volatile memory cell. For example, applying a fixed control gate voltage to the control gate of a non-volatile memory cell with an unknown threshold voltage may lead to an electrical response corresponding to the linear region of a non-volatile memory cell having a low threshold voltage or to an electrical response in the saturation region of the underlying MOS device for a non-volatile memory cell having a higher threshold voltage. Operating from the linear region to the saturation region, the electrical response phasing between adjacent non-volatile memory cell threshold voltage levels will not be uniform over the full range of possible responses of the non-volatile memory cell.
The electrical response distribution of a non-volatile memory array after programming also depends on the non-uniform response characteristics of the array's MOS transistors due to different operating regions corresponding to different threshold voltage levels of these MOS transistors. Uneven separation between the electrical responses as a function of the threshold voltage levels leads to a distribution of responses from the memory cells which are dependent on the threshold levels. This uneven distribution hinders the capability to resolve more threshold voltage levels in a single non-volatile memory cell. Therefore, the available range of threshold voltage levels which can be programmed is limited due to limits on the applicable fixed gate voltages that can be used to read out the non-volatile memory cells in the prior art.